? semiconductor components industries, llc, 2015 january, 2015 ? rev. 1 1 publication order number: nss60101dmt/d nss60101dmt 60 v, 1 a, low v ce(sat) npn transistors on semiconductor?s e 2 poweredge family of low v ce(sat) transistors are miniature surface mount devices featuring ultra low saturation voltage (v ce(sat) ) and high current gain capability. these are designed for use in low voltage, high speed switching applications where affordable efficient energy control is important. typical applications are dc?dc converters and led lightning, power management etc. in the automotive industry they can be used in air bag deployment and in the instrument cluster. the high current gain allows e 2 poweredge devices to be driven directly from pmu?s control outputs, and the linear gain (beta) makes them ideal components in analog amplifiers. features ? nsv prefix for automotive and other applications requiring unique site and control change requirements; aec?q101 qualified and ppap capable ? NSV60101DMTWTBG ? w ettable flanks device ? these devices are pb?free, halogen free/bfr free and are rohs compliant maximum ratings (t a = 25 c) rating symbol max unit collector?emitter voltage v ceo 60 vdc collector?base voltage v cbo 60 vdc emitter?base voltage v ebo 6 vdc collector current ? continuous i c 1 a collector current ? peak i cm 2 a stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. thermal characteristics characteristic symbol max unit thermal resistance junction?to?ambient (notes 1 and 2) r ja 55 c/w total power dissipation per package @ t a = 25 c (note 2) p d 2.27 w thermal resistance junction?to?ambient (note 3) r ja 69 c/w power dissipation per transistor @ t a = 25 c (note 3) p d 1.8 w junction and storage temperature range t j , t stg ?55 to +150 c 1. per jesd51?7 with 100 mm 2 pad area and 2 oz. cu (dual operation). 2. p d per t ransistor when both are turned on is one half of total p d or 1.13 w atts. 3. per jesd51?7 with 100 mm 2 pad area and 2 oz. cu (single?operation). www. onsemi.com an = specific device code m = date code = pb?free package an m 1 2 3 6 5 4 wdfn6 case 506an marking diagram 1 pin connections device package shipping ? ordering information nss60101dmttbg wdfn6 (pb?free) 3000/tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. (note: microdot may be in either location) NSV60101DMTWTBG wdfn6 (pb?free) 3000/tape & reel 60 volt, 1 amp npn low v ce(sat) transistors
nss60101dmt www. onsemi.com 2 table 1. electrical characteristics (t a = 25 c unless otherwise noted) characteristic symbol min typ max unit off characteristics collector?emitter breakdown voltage (i c = 10 ma, i b = 0) v (br)ceo 60 v collector?base breakdown voltage (ic = 0.1 ma, i e = 0) v (br)cbo 80 v emitter?base breakdown voltage (i e = 0.1 ma, i c = 0) v (br)ebo 6 v collector cutoff current (v cb = 60 v, i e = 0) i cbo 100 na emitter cutoff current (v be = 5.0 v) i ebo 100 na on characteristics dc current gain (note 4) (i c = 100 ma, v ce = 2.0 v) (i c = 500 ma, v ce = 2.0 v) (i c = 1 a, v ce = 2.0 v) (i c = 2 a, v ce = 2.0 v h fe 150 120 90 35 250 240 180 55 collector?emitter saturation voltage (note 4) (i c = 500 ma, i b = 50 ma) (i c = 1 a, i b = 50 ma) (i c = 1 a, i b = 100 ma) v ce(sat) 0.063 0.130 0.115 0.100 0.200 0.180 v base emitter saturation voltage (note 4) (i c = 500 ma, i b = 50 ma) (i c = 1 a, i b = 50 ma) (i c = 1 a, i b = 100 ma) v be(sat) 1.0 1.0 1.1 v base?emitter turn?on voltage (note 4) (i c = 500 ma, v ce = 2 v) v be(on) 0.9 v dynamic characteristics output capacitance (v cb = 10 v, f = 1.0 mhz) c obo 10 pf cutoff frequency (i c = 50 ma, v ce = 2.0 v, f = 100 mhz) f t 180 mhz switching times delay time (v cc = 10 v, i c = 0.5 a, i b1 = 25 ma, i b2 = ?25 ma) t d 13 ns rise time (v cc = 10 v, i c = 0.5 a, i b1 = 25 ma, i b2 = ?25 ma) t r 18 ns storage time (v cc = 10 v, i c = 0.5 a, i b1 = 25 ma, i b2 = ?25 ma) t s 700 ns fall time (v cc = 10 v, i c = 0.5 a, i b1 = 25 ma, i b2 = ?25 ma) t f 80 ns product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 4. pulse condition: pulse width = 300 sec, duty cycle 2%
nss60101dmt www. onsemi.com 3 typical characteristics figure 1. dc current gain figure 2. dc current gain i c , collector current (a) i c , collector current (a) 10 1 0.1 0.01 0.001 0 50 100 150 200 300 350 400 10 1 0.1 0.01 0.001 0 50 100 150 200 250 350 400 figure 3. collector current as a function of collector emitter voltage figure 4. collector?emitter saturation voltage v ce , collector emitter voltage (v) i c , collector current (a) 6 5 4 3 2 1 0 0 0.2 0.6 0.8 1.2 1.6 1.8 2.2 10 1 0.1 0.01 0.001 0.01 0.1 1 figure 5. collector?emitter saturation voltage figure 6. base?emitter saturation voltage i c , collector current (a) i c , collector current (a) 1 0.1 0.01 0.001 0.01 0.1 1 10 0.1 0.01 0.001 0 0.5 1.0 h fe , dc current gain h fe , dc current gain i c , collector current (a) v ce(sat) , collector?emitter saturation (v) v ce(sat) , collector?emitter saturation (v) v be(sat) , base?emitter saturation (v) 250 v ce = 2 v 150 c 100 c 25 c ?55 c 300 v ce = 5 v 150 c 100 c 25 c ?55 c 0.4 1.0 1.4 2.0 i b = 20 ma 2.0 ma 4.0 ma 6.0 ma 8.0 ma 10 ma 12 ma 14 ma 16 ma 18 ma i c /i b = 50 150 c 100 c 25 c ?55 c i c /i b = 100 150 c 100 c 25 c ?55 c 150 c 100 c 25 c ?55 c 450 450 1 i c /i b = 20
nss60101dmt www. onsemi.com 4 typical characteristics figure 7. base?emitter ?on? voltage figure 8. collector saturation region i c , collector current (a) i b , base current (a) 10 1 0.1 0.01 0.001 0 0.4 1.0 1 0.1 0.01 0.001 0 0.1 0.4 0.5 0.7 0.9 1.0 figure 9. input capacitance figure 10. output capacitance v eb , base?emitter voltage (a) v cb , collector?base reverse voltage (v) 7 5 3 1 0 40 120 240 30 25 20 15 10 5 0 0 5 15 20 30 35 figure 11. f t , current gain bandwidth product figure 12. power derating i c , collector current (ma) temperature ( c) 1000 100 10 1 10 100 1000 150 125 100 75 50 25 0 0 0.5 1.0 1.5 2.0 2.5 v be(on) , base?emitter voltage (v) v ce(sat) , collector?emitter saturation (v) c ibo , input capacitance (pf) c obo , output capacitance (pf) f t , current gain bandwidth product (mhz) p d , power dissipation (w) 150 c 100 c 25 c ?55 c v ce = 2 v 80 160 200 i c = 2.0 a i c = 1.0 a i c = 0.5 a i c = 0.1 a 10 25 40 t a = 25 c f = 1 mhz t j = 25 c v ce = 2 v f test = 100 mhz 0.2 0.6 0.8 1.2 t a = 25 c 0.0001 0.2 0.3 0.6 0.8 246 t a = 25 c f = 1 mhz
nss60101dmt www. onsemi.com 5 typical characteristics figure 13. thermal resistance by transistor t, pulse time (sec) 0.000001 0.1 1 10 100 r(t), effective transient thermal resistance ( c/w) 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 single pulse 0.01 0.02 0.05 0.10 0.20 duty cycle = 0.5 figure 14. thermal resistance for both transistors t, pulse time (sec) 0.000001 0.1 1 10 100 r(t), effective transient thermal resistance ( c/w) 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 single pulse 0.01 0.02 0.05 0.10 0.20 duty cycle = 0.5
nss60101dmt www. onsemi.com 6 package dimensions notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from the terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. seating plane d e 0.10 c a3 a a1 0.10 c wdfn6 2x2, 0.65p case 506an issue f dim a min max millimeters 0.70 0.80 a1 0.00 0.05 a3 0.20 ref b 0.25 0.35 d 2.00 bsc d2 0.57 0.77 0.90 1.10 e 2.00 bsc 0.25 ref e2 e 0.65 bsc k 0.20 0.30 l 0.15 bsc f pin one reference 0.08 c 0.10 c note 4 a 0.10 c note 3 l e d2 e2 b b 3 6 6x 1 k 4 0.05 c d2 f mounting footprint bottom view soldermask defined dimensions: millimeters l1 detail a l optional constructions ?? ??? ??? --- 0.10 l1 a 0.10 cb a 0.10 cb 6x 0.47 2.30 1.10 0.77 2x 1.74 0.65 pitch 6x 0.35 1 package outline on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 nss60101dmt/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative
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